The following U.S. patents are believed to represent the current state of the art: U.S. Pat. Nos. 6,331,790, 6,194,912, 5,666,288, 6,490,707 and 6,301,696. These patents all relate to prior art with respect to the current patent.
U.S. Pat. Nos. 6,331,790, and 6,184,912 describe semiconductor devices, which contain logic cells that further contain look up tables and interconnects, which may be patterned by a single via mask. The advantages of such application-specific integrated circuits (ASICs) have been clearly defined in the prior art. Other of the above patents describe methods for converting field programmable gate array (FPGA) devices into mask defined devices called application specific integrated circuits (ASICs). By their very nature these methods convert the programmable interconnect information of an FPGA design into some corresponding mask based information for the equivalent ASIC design, but do not deal with the verification and modeling of single via mask customization.
In both ASICs and FPGAs, it is common to provide a library of components, from which the designer may select and instantiate into a design. That is, a library component may be used as portion of a design of a device. In ASICs, these library components are typically implemented out of custom designed transistors and metal interconnects that require a full set of masks to fabricate. In FPGAs, these components are typically implemented by configuring a fixed preexisting set of switches and logic functions. In either case, appropriate functional, physical and timing models may be generated for the library of components in order for the user to verify the function, layout and timing of their design. In ASICs, this may be done by designing the specific transistors and metal interconnects for the component and extracting the necessary library information from implementations and simulations of that component design. In FPGAs a basic template or cell may be custom designed, from which the basic physical and timing information may be obtained. The specific functional, physical and timing models of a component are then derived from implementation and simulation of the configured cell or cells of the component.
In U.S. Pat. No. 6,490,707, granted Dec. 3, 2002, Baxter teaches a way to convert FPGAs into ASICs by replacing the interconnect transistors that are used with actual via connections. Similarly, Lien et al., in U.S. Pat. No. 6,301,696, granted Oct. 9, 2001, also teach techniques for replacing programmable interconnect transistors with via connections. Finally, Jones et al. teach, in U.S. Pat. No. 5,666,288, granted Sep. 9, 1997, methods for modifying libraries of cells to optimize for size, timing and power consumption.
In contrast to this prior art, embodiments of the current invention provide a method for creating models for components by modeling the set of customizable vias. In this way, techniques employed in FPGA library generation may be applied to the modeling of ASIC library elements and designs, which may be a particularly useful technique when the ASIC, such as one of those described in the prior art discussed above, has fixed interconnects with customization limited to one or more via layers.
Furthermore, the process of customizing an ASIC with a specific design such that it properly performs the function of that design is a complex task that can be prone to error. Verification of the resulting customized design is currently a computationally intensive process of extracting the circuit level design from the physical mask data and simulating with external stimuli to ensure it will function as intended. By contrast, embodiments of the current invention may provide a way to generate the circuit level design of a specific customization by exchanging unselected via models within an un-customized design with selected via models according to the customized via information.